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integrated silicon solution, inc. ? www.issi.com 1 rev. d 06/21/2011 copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. is61wv12816dall/dals is61wv12816dbll/dbls is64wv12816dbll/dbls features high speed: (is61/64wv12816dall/dbll) ? high-speed access time: 8, 10, 12, 20 ns ? low active power: 135 mw (typical) ? low standby power: 12 w (typical) cmos standby low power: (is61/64wv12816dals/dbls) ? high-speed access time: 25, 35 ns ? low active power: 55 mw (typical) ? low standby power: 12 w (typical) cmos standby ? single power supply ? v dd 1.65v to 2.2v (is61wv12816daxx) ? v dd 2.4v to 3.6v (is61/64wv12816dbxx) ? fully static operation: no clock or refresh required ? three state outputs ? data control for upper and lower bytes ? industrial and automotive temperature support ? lead-free available 128k x 16 high speed asynchronous cmos static ram description the issi is61wv12816daxx/dbxx and is64wv12816dbxx are high-speed, 2,097,152-bit static rams organized as 131,072 words by 16 bits. it is fabricated using issi 's high- performance cmos technology. this highly reliable pro- cess coupled with innovative circuit design techniques, yields high-performance and low power consumption de- vices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory. a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the is61wv12816daxx/dbxx and is64wv12816dbxx are packaged in the jedec standard 44-pin tsop type ii and 48-pin mini bga (6mm x 8mm). functional block diagram a0-a16 ce oe we 128k x 16 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb july 2011
2 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 ce i/o0 i/o1 i/o2 i/o3 v dd gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd v dd i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 nc 44-pin tsop (type ii) (t) pin descriptions a0-a16 address inputs i/o0-i/o15 d ata inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground truth table i/o pin mode we we we we we ce ce ce ce ce oe oe oe oe oe lb lb lb lb lb ub ub ub ub ub i/o0-i/o7 i/o8-i/o15 v dd current not selected x h x x x high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc x l x h h high-z high-z read h l l l h d out high-z i cc h l l h l high-z d out hllll d out d out write l l x l h d in high-z i cc l l x h l high-z d in llxll d in d in pin configuration
integrated silicon solution, inc. ? www.issi.com 3 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls pin descriptions a0-a16 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection v dd power gnd ground 48-pin mini bga (b) pin configuration 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 nc i/o 8 ub a3 a4 ce i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 nc a7 i/o 3 v dd v dd i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc
4 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls dc electrical characteristics (over operating range) v dd = 2.4v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 1.8 ? v v ol output low voltage v dd = min., i ol = 1.0 ma ? 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width < 10 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 3.3v + 5% symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width < 10 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 1.65v-2.2v symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 ? v v ol output low voltage i ol = 0.1 ma 1.65-2.2v ? 0.2 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v v il (1) input low voltage 1.65-2.2v ?0.2 0.4 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width < 10 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width < 10 ns). not 100% tested.
integrated silicon solution, inc. ? www.issi.com 5 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls ac test loads figure 1. r1 5 pf including jig and scope r2 output vtm figure 2. z o = 50 vdd/2 50 output 30 pf including jig and scope ac test conditions parameter unit unit unit (2.4v-3.6v) (3.3v + 5%) (1.65v-2.2v) input pulse level 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v 0.4v to v dd - 0.3v input rise and fall times 1v/ ns 1v/ ns 1v/ ns input and output timing vdd /2 vdd + 0.05 0.9v and reference level (v ref ) 2 output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2 r1 ( ) 1909 317 13500 r2 ( ) 1105 351 10800 v tm (v) 3.0v 3.3v 1.8v
6 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd + 0.5 v v dd v dd relates to gnd ?0.3 to 4.0 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c i/o input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v.
integrated silicon solution, inc. ? www.issi.com 7 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls operating range (v dd ) (is61wv12816dbll) (1) range ambient temperature v dd (8 n s ) 1 v dd (10 n s ) 1 commercial 0c to +70c 3.3v + 5% 2.4v-3.6v industrial ?40c to +85c 3.3v + 5% 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 10ns. when operated in the range of 3.3v + 5%, the device meets 8ns. operating range (v dd ) (is64wv12816dbll) (2,3) range ambient temperature v dd (10 n s ) 2 v dd (12 n s ) 2 automotive ?40c to +125c 3.3v + 5% 2.4v-3.6v note: 2. when operated in the range of 2.4v-3.6v, the device meets 12ns. when operated in the range of 3.3v + 5%, the device meets 10ns. 3. if the device is operated in the temperature range of -40 o c to +85 o c, the device meets 10ns. high speed (is61wv12816dall/dbll) operating range (v dd ) (is61wv12816dall) range ambient temperature v dd speed commercial 0c to +70c 1. 65v-2. 2v 20ns industrial ?40c to +85c 1. 65v-2. 2v 20ns automotive ?40c to +125c 1. 65v-2. 2v 20ns power supply characteristics (1) (over operating range) -8 -10 -12 -20 symbol parameter test conditions min. max. min. max. min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. ? 65 ? 60 ? 55 ? 40 ma supply current i out = 0 ma, f = f max ind. ? 70 ? 65 ? 55 ? 45 ce = v il auto. (3) ?? ?75 ? 60 ?50 v in v dd ? 0.3v, or typ. (2) 45 45 v in 0.4v i cc 1 operating v dd = max., com. ? 2 ? 2 ? 2 ? 2 ma supply current i out = 0 ma, f = 0 ind. ? 2 ? 2 ? 2 ? 2 ce = v il auto. ? ? ? 2 ? 2 ? 2 v in v dd ? 0.3v, or v in 0.4v i sb 2 cmos standby v dd = max., com. ? 50 ? 50 ? 50 ? 50 a current (cmos inputs) ce v dd ? 0.2v, ind. ? 70 ? 70 ? 70 ? 70 v in v dd ? 0.2v, or auto. ? ? ? 100 ? 100 ? 100 v in 0.2v , f = 0 typ. (2) 4 4 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. 3. for automotive grade at 15ns, typ. icc = 38ma, not 100% tested.
8 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls power supply characteristics (1) (over operating range) -25 -35 -45 symbol parameter test conditions min. max. min. max. min. max. unit i cc v dd dynamic operating v dd = max., com. ? 20 ? 20 ? 18 ma supply current i out = 0 ma, f = f max ind. ? 25 ? 25 ? 20 ce = v il auto. ? 40 ? 35 ? 30 v in v dd ? 0.3v, or typ. (2) 18 v in 0.4v i cc 1 operating v dd = max., com. ? 2 ? 2 ? 2 ma supply current i out = 0 ma, f = 0 ind. ? 2 ? 2 ? 2 ce = v il auto. ? 2 ? 2 ? 2 v in v dd ? 0.3v, or v in 0.4v i sb 2 cmos standby v dd = max., com. ? 40 ? 40 ? 40 a current (cmos inputs) ce v dd ? 0.2v, ind. ? 50 ? 50 ? 50 v in v dd ? 0.2v, or auto. ? 75 ? 75 ? 75 v in 0.2v , f = 0 typ. (2) 4 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. operating range (v dd ) (is61wv12816dbls) range ambient temperature v dd (35 n s ) commercial 0c to +70c 2.4v-3.6v industrial ?40c to +85c 2.4v-3.6v low power (is61wv12816dals/dbls) operating range (v dd ) (is61wv12816dals) range ambient temperature v dd speed commercial 0c to +70c 1. 65v-2. 2v 45ns industrial ?40c to +85c 1. 65v-2. 2v 45ns automotive ?40c to +125c 1. 65v-2. 2v 55ns operating range (v dd ) (is64wv12816dbls) range ambient temperature v dd (35 n s ) automotive ?40c to +125c 2.4v-3.6v
integrated silicon solution, inc. ? www.issi.com 9 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls read cycle switching characteristics (1) (over operating range) -8 -10 -12 symbol parameter min. max. min. max. min. max. unit t rc read cycle time 8 ? 10 ? 12 ? ns t aa address access time ? 8 ? 10 ? 12 ns t oha output hold time 2.0 ? 2.0 ? 3 ? ns t ace ce access time ? 8 ? 10 ? 12 ns t doe oe access time ? 5.5 ? 6.0 ? 6.0 ns t hzoe (2) oe to high-z output ? 3 ? 4 ? 6 ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? ns t hzce (2 ce to high-z output 0 3 0 4 0 6 ns t lzce (2) ce to low-z output 3 ? 3 ? 3 ? ns t ba lb , ub access time ? 5.5 ? 6.5 ? 6.5 ns t hzb (2) lb , ub to high-z output 0 5.5 0 6.5 0 6.5 ns t lzb (2) lb , ub to low-z output 0 ? 0 ? 0 ? ns t pu power up time 0 ? 0 ? 0 ? ns t pd power down time ? 8 ? 10 ? 10 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage.
10 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls read cycle switching characteristics (1) (over operating range) -20 ns -25 ns -35 ns -45 ns symbol parameter min. max. min. max. min. max. min. max. unit t rc read cycle time 20 ? 25 ? 35 ? 45 ? ns t aa address access time ? 20 ? 25 ? 35 ? 45 ns t oha output hold time 2.5 ? 6 ? 8 ? 10 ? ns t ace ce access time ? 20 ? 25 ? 35 ? 45 ns t doe oe access time ? 8 ? 12 ? 15 ? 20 ns t hzoe (2) oe to high-z output 0 8 0 8 0 10 0 15 ns t lzoe (2) oe to low-z output 0 ? 0 ? 0 ? 0 ? ns t hzce (2 ce to high-z output 0 8 0 8 0 10 0 15 ns t lzce (2) ce to low-z output 3 ? 10 ? 10 ? 10 ? ns t ba lb , ub access time ? 8 ? 25 ? 35 ? 45 ns t hzb lb , ub to high-z output 0 8 0 8 0 10 0 15 ns t lzb lb , ub to low-z output 0 ? 0 ? 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25v, input pulse levels of 0.4 v to v dd -0.3v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
integrated silicon solution, inc. ? www.issi.com 11 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls data valid read1.eps previous data valid t aa t oha t oha t rc d out address ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il , ub or lb = v il ) t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ub_cedr2.eps t hzb address oe ce lb, ub d out t hzce t ba t lzb t rc t pd i sb i cc 50% v dd supply current 50% t pu read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce , ub , or lb = v il . 3. address is valid prior to or coincident with ce low transition.
12 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls write cycle switching characteristics (1,3) (over operating range) -8 -10 -12 symbol parameter min. max. min. max. min. max. unit t wc write cycle time 8 ? 10 ? 12 ? ns t sce ce to write end 6.5 ? 8 ? 9 ? ns t aw address setup time 6.5 ? 8 ? 9 ? ns to write end t ha address hold from write end 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? ns t pwb lb , ub valid to end of write 6.5 ? 8 ? 9 ? ns t pwe 1 we pulse width 6.5 ? 8 ? 9 ? ns t pwe 2 we pulse width ( oe = low) 8.0 ? 10 ? 11 ? ns t sd data setup to write end 5 ? 6 ? 9 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 3.5 ? 5 ? 6 ns t lzwe (2) we high to low-z output 2 ? 2 ? 3 ? ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0v to 3.0v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. shaded area product in development
integrated silicon solution, inc. ? www.issi.com 13 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls write cycle switching characteristics (1,2) (over operating range) -20 ns -25 ns -35 ns -45ns symbol parameter min. max. min. max. min. max. min. max. unit t wc write cycle time 20 ? 25 ? 35 ? 45 ? ns t sce ce to write end 12 ? 18 ? 25 ? 35 ? ns t aw address setup time 12 ? 15 ? 25 ? 35 ? ns to write end t ha address hold from write end 0 ? 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? 0 ? ns t pwb lb , ub valid to end of write 12 ? 18 ? 30 ? 35 ? ns t pwe 1 we pulse width ( oe = high) 12 ? 18 ? 30 ? 35 ? ns t pwe 2 we pulse width ( oe = low) 17 ? 20 ? 30 ? 35 ? ns t sd data setup to write end 9 ? 12 ? 15 ? 20 ? ns t hd data hold from write end 0 ? 0 ? 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 9 ? 12 ? 20 ? 20 ns t lzwe (3) we high to low-z output 3 ? 5 ? 5 ? 5 ? ns notes: 1. test conditions for is61wv6416ll assume signal transition times of 1.5ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v dd -0.3v and output loading specified in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
14 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls write cycle no. 2 ( we controlled. oe is high during write cycle) (1,2) data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd ub_cewr2.eps notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = ( ce ) [ ( lb ) = ( ub ) ] ( we ). ac waveforms write cycle no. 1 ( ce controlled, oe is high or low) (1 ) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in data in valid t lzwe t sd ub_cewr1.eps
integrated silicon solution, inc. ? www.issi.com 15 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls ac waveforms write cycle no. 3 ( we controlled. oe is low during write cycle) (1) data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd ub_cewr3.eps write cycle no. 4 ( lb , ub controlled, back-to-back write) (1,3) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 ub_cewr4.eps t hd t sa t hzwe address ce ub, lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha notes: 1. the internal write time is defined by the overlap of ce = low, ub and/or lb = low, and we = low. all signals must be in valid states to initiate a write, but any can be deasserted to terminate the write. the t sa , t ha , t sd , and t hd timing is referenced to the rising or falling edge of the signal that terminates the write. 2. tested with oe high for a minimum of 4 ns before we = low to place the i/o in a high-z state. 3. we may be held low across many address cycles and the lb , ub pins can be used to control the write function.
16 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls data retention waveform ( ce controlled) high speed (is61wv12816dall/dbll) data retention switching characteristics (2.4v-3.6v) symbol parameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 ? 3.6 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v com. ? 10 50 a ind. ? ? 70 auto. 100 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ??ns note 1 : typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode data retention switching characteristics (1.65v-2.2v) symbol parameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 1.2 ? 3.6 v i dr data retention current v dd = 1.2v, ce v dd ? 0.2v com. ? 10 50 a ind. ? ? 70 auto. ? ? 100 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ??ns note 1 : typical values are measured at v dd = 1.8v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. ? www.issi.com 17 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls data retention waveform ( ce controlled) low power (is61wv12816dals/dbls) data retention switching characteristics (2.4v-3.6v) symbol p arameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 2.0 ? 3.6 v i dr data retention current v dd = 2.0v, ce v dd ? 0.2v com. ? 20 40 a ind. ? ? 50 auto. 75 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ??ns note 1 : typical values are measured at v dd = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode data retention switching characteristics (1.65v-2.2v) symbol p arameter test condition options min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 1.2 ? 3.6 v i dr data retention current v dd = 1.2v, ce v dd ? 0.2v com. ? 20 40 a ind. ? ? 50 auto. ? ? 75 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ??ns note 1 : typical values are measured at v dd = 1.8v, t a = 25 o c and not 100% tested.
18 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls ordering information (high speed) commercial range: 0c to +70c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 (8 1 ) is61wv12816dbll-10tl tsop (type ii), lead-free note: 1. speed = 8ns for v dd = 3.3v + 5%. speed = 10ns for v dd = 2.4v to 3.6v. industrial range: -40c to +85c voltage range: 2.4v to 3.6v speed (ns) order part no. package 10 (8 1 ) is61wv12816dbll-10bi 48 mini bga (6mm x 8mm) is61wv12816dbll-10bli 48 mini bga (6mm x 8mm), lead-free is61wv12816dbll-10ti tsop (type ii) is61wv12816dbll-10tli tsop (type ii), lead-free note: 1. speed = 8ns for v dd = 3.3v + 5%. speed = 10ns for v dd = 2.4v to 3.6v. industrial range: -40c to +85c voltage range: 1.65v to 2.2v speed (ns) order part no. package 20 is61wv12816dall-20bi 48 mini bga (6mm x 8mm) is61wv12816dall-20ti tsop (type ii) automotive range: -40c to +125c voltage range: 2.4v to 3.6v speed (ns) order part no. package 12 (10 2,3 ) is64wv12816dbll-12ba3 48 mini bga (6mm x 8mm) is64wv12816dbll-12bla3 48 mini bga (6mm x 8mm), lead-free is64wv12816dbll-12cta3 tsop (type ii), copper leadframe is64wv12816dbll-12ctla3 tsop (type ii), lead-free, copper leadframe note: 2. speed = 10ns for v dd = 3.3v + 5%. speed = 12ns for v dd = 2.4v to 3.6v. 3. speed = 10ns for v dd = 2.4v to 3.6v and temperature = -40 o c to +85 o c.
integrated silicon solution, inc. ? www.issi.com 19 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls ordering information (low power - in evaluation) industrial range: -40c to +85c voltage range: 2.4v to 3.6v speed (ns) order part no. package 35 is61wv12816dbls-35tli tsop (type ii), lead-free
20 integrated silicon solution, inc. ? www.issi.com rev. d 06/21/2011 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline
integrated silicon solution, inc. ? www.issi.com 21 rev. d 06/21/2011 1 2 3 4 5 6 7 8 9 10 11 12 is61wv12816dall/dals, is61wv12816dbll/dbls, is64wv12816dbll/dbls 2. dimension d and e1 do not include mold protrusion. 3. dimension b does not include dambar protrusion/intrusion. 1. controlling dimension : mm note : 06/04/2008 package outline

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